Wafer manufacturing method, polishing apparatus, and wafer

ABSTRACT

The present invention provides a wafer manufacturing method and a wafer polishing apparatus which enable control of sags in a periphery of a wafer and improvement of nanotopology values thereof that is strongly required recently, and a wafer. In a polishing process for making a mirror surface of the wafer, a back surface of the wafer is polished to produce a reference plane thereof.

TECHNICAL FIELD

The present invention relates to a wafer manufacturing method, apolishing apparatus, and a wafer, more particularly to a wafermanufacturing method and a polishing apparatus which prevent peripheralsags of a mirror polished wafer so that the wafer can be polished up toits peripheral edge at a high flatness level, and a wafer.

BACKGROUND ART

Generally a silicon wafer manufacturing method comprises, as shown inFIG. 18( a), a slicing step 100 of slicing a single crystal ingot toobtain a thin disk-shaped wafer; a chamfering step 102 of chamfering aperipheral edge portion of the wafer obtained through the slicing step100 to prevent cracking and chipping of the wafer; a lapping step 104 offlattening this wafer; an etching step 106 of removing processingdeformation remaining in the so chamfered and lapped wafer; a polishingstep 108 of making a mirror surface of the wafer; and a cleaning step110 of cleaning the polished wafer to remove a polishing agent or dustparticles deposited thereon. The main steps are only listed above, andsometimes other steps such as a heat treatment step and a surfacegrinding step may be added, or the step sequence may be changed.

The polishing step 108 of making a mirror surface of the wafer isfurther classified into sub-steps, and various types of polishingmethods and polishing apparatus are used in each of the sub-steps. As awafer single side polishing apparatus 200 used in the polishing process,for instance, as shown in FIG. 14, there has been widely known apolishing apparatus comprising a disk-shaped turn table 206 which isrotated by a rotary shaft 204 and has a polishing cloth 202 adhered onthe upper surface thereof, a wafer holding head (polishing head) 208 forholding one surface of a wafer (W) to be polished and contacting anothersurface of the wafer (W) to the polishing cloth 202, and a head drivingmechanism 210 for operating relative rotation of the wafer holding head208 against the turn table 206, wherein the wafer is polished bysupplying slurry 214 containing abrasive grains from a slurry supplyingunit 212 between the polishing cloth 202 and the wafer (W).

As another type of polishing, as shown in FIG. 15, there is a method ofsimultaneously polishing both the front and back surfaces of a wafer.This double side polishing apparatus 220 has a lower polishing turntable 222 and an upper polishing turn table 224 which are faced eachother vertically. A lower polishing cloth 226 is adhered on the uppersurface of the lower polishing turn table 222, and an upper polishingcloth 228 is adhered on the lower surface of the upper polishing turntable 224.

A disk-shaped carrier 230 is supported between the upper surface of thelower polishing cloth 226 of the lower polishing turn table 222 and thelower surface of the upper polishing cloth 228 of the upper polishingturn table 224 and rotates and revolves slidably between the lowerpolishing cloth 226 and the upper polishing cloth 228. The carrier 230has a plurality of wafer holes 232.

Wafers (W) to be polished are set in the wafer holes 232. When thewafers (W) are polished, a polishing agent is supplied between thewafers (W) and the polishing cloths 226, 228 via throughholes (notshown) formed in the upper polishing turn table 224 from nozzles (notshown). As the carrier 230 rotates and revolves, the wafers (W) rotateand revolve slidably between the lower polishing cloth 226 and the upperpolishing cloth 228, thereby both the surfaces of the wafers (W) beingpolished.

There are also various methods of holding a wafer. For instance, thereare a batch holding method in which a plurality of wafers are adhered onone and the same plate using wax or the like and are polished, and asingle wafer holding method in which wafers are held one by one by meansof wax or vacuum chucking and are polished.

The wafer holding method employed when polishing a wafer is dividedbroadly into two systems, that is, a wax mounting system and a waxlesssystem. The waxless system comprises a vacuum chucking system, atemplate system, and the like.

Of these systems, as shown in FIG. 17, a wafer holding head 240according to the template system has such a structure as, when polishinga wafer (W), the wafer (W) is fitted in an engagement hole 244 in atemplate blank of the template 242, and the back surface of the wafer(W) is held by a backing pad 250 adhered to a lower surface of the upperpolishing turn table 248 attached to a lower end of a head 246.

When polishing wafers (W) with the holding head 240, wafers to bepolished are fitted into each of the engagement holes 244 in thetemplate blank of the template 242, respectively, and the thus situatedtemplate 242 is arranged on a lower polishing turn table (not shown) sothat the wafers (W) are in lower positions. In this state, one surfaceof the wafer (W) contacts a polishing cloth adhered on the lowerpolishing turn table (not shown). In this state, when a back pressure isapplied to the template 242 by the upper polishing turn table 248 and atthe same time the lower polishing plate (not shown) is rotated, thetemplate 242 rotates at the place together with the lower polishingplate and the wafer (W) is polished.

Thus there is known a holding method named a waxless system in which,without using vacuum chucking or adhesion by wax, a soft material nameda backing pad is used for holding a wafer. Also there is a polishingmethod named CMP (Chemical and Mechanical Polishing) in which a wafer ispolished in such a manner as the wafer is held by a soft backing pad notto transfer a vacuum chucking side configuration of the wafer to a frontsurface thereof.

With a combination of various types of polishing apparatus describedabove, a wafer is mirror polished by multistage polishing includingprimary polishing, secondary polishing, final polishing, and the like.

Currently, the wax mounting system is often used in the above mentionedpolishing systems, but in view of deterioration of a flatness level dueto variations in an adhesive layer, cleaning of the wax, and so forth,for instance, polishing of the waxless system, double side polishing orthe like have also been employed. For instance, as shown in FIG. 18 (b),a waxless polishing step 108A shows a case in which polishing of thewaxless system is performed in all of a primary polishing step (A1), asecondary polishing step (A2), and a final polishing step (A3), while adouble side polishing step 108B shows a case in which double sidepolishing is performed in a primary polishing step (B1) and polishing ofother systems are employed in a secondary polishing step (B2) and afinal polishing step (B3).

The primary polishing step (A1), (B1) is for the main purpose offlattening and making a mirror surface, and is a step of polishing awafer with the stock removal of 10 μm or more. A relatively hardpolishing cloth may be used for correcting a wafer configuration(so-called correction polishing). Recently, before a polishing step, aflatness level of a wafer is improved by, for instance, an etching step,a lapping step prior to the etching step, or a surface grinding step,and with keeping this improved configuration, making a mirror surface(so-called copy polishing) may be performed. The combination ofcorrection polishing and copy polishing may improve a flatness level ofa wafer and make a mirror surface thereof.

The secondary polishing step (A2), (B2) is for the main purpose ofmaking a mirror surface of the portion which has not been improved inthe primary polishing step (A1), (B1), and in the secondary polishingstep, there is mainly performed so-called copy polishing wherein a waferis polished with keeping a wafer configuration by removing a certainthickness with the stock removal of several μm. In this stage, there aresome cases where a configuration of a peripheral portion of a wafer iscorrected.

The final polishing step (A3), (B3) is for the purpose of improvinghaze, and the stock removal is of a very small amount.

In order to improve a flatness level more by removing tapers and thelike of a wafer, it is effective to polish the wafer while rotating itduring the polishing operation, and the waxless polishing or the doubleside (simultaneous) polishing is preferable. Therefore, these systems ofpolishing may be performed in the primary polishing step and so on.

When a wafer is polished by the conventional waxless polishing or doubleside (simultaneous) polishing, although tapers are improved, a number ofperipheral sags are generated. Further while the wafer is polished inmultiple polishing stages, rises and the like are generated to forminflection points on a wafer surface, especially in peripheral portionsthereof, and make irregularities in a minute area (may be termednanotopology) or flatness thereof worse.

The peripheral sags described above are due to a phenomenon wherein theperiphery of the wafer is polished excessively and becomes thinner thanthe central portion thereof in terms of thickness. This phenomenoneasily occurs when polishing a wafer by a general method.

The rises are due to a phenomenon wherein the periphery of the wafer isnot polished and becomes thicker than the central portion. Thisphenomenon seldom occurs usually, but often occurs when a wafer ispolished with a polishing head using a retainer ring in CMP and thelike.

The rises may also be generated when the polishing rate is intentionallyslowed down in the wafer periphery by, for instance, making thepolishing pressure lower only in the periphery than in the centralportion to improve the flatness level in the primary or secondarypolishing step (on the assumption that peripheral sags are generated).

The inflection points are formed when a wafer having the peripheral sagsis polished in the above described manner that the rises are generated.The presence of the inflection points makes the value termednanotopology worse.

The nanotopology (may be also termed nanotopography) is one of surfaceevaluation wherein a wafer surface is divided into a plurality of areasand a variation in undulations (peak to valley: PV value) for each ofthe areas is evaluated. The evaluation is carried out as to whether whatpercentage of the wafer surface is occupied by the areas having thespecified variation in undulations (PV value) or what extent is themaximum PV value among the PV values for all the evaluated areas.

The flatness is based on a back side reference, a front side reference,etc., and expressed, for instance, as SBIR or SFQR. Here, the SBIR (SiteBack side Ideal Range) is defined as a difference in the distancebetween the highest position and the lowest position from a vacuumchucking face which vacuum chucks and fixes a wafer, when assuming thechucking face as a fixed reference for flatness and evaluating each site(each area obtained by dividing the entire surface of a wafer intorespective prescribed areas).

On the other hand, the SFQR (Site Front least-sQuares Range) is a valueexpressing a maximum range of irregularities against an average plane ofa front side reference in terms of flatness, the average plane beingcalculated for each site. As to the wafer flatness, it is necessary toimprove the SFQR and nanotopology of the front side reference.

When a wafer is subjected to the double side polishing only, although aninflection point is not formed, sags are easily generated in theperiphery of the wafer. Especially, the sags are generated on bothsurfaces of the wafer, and hence there is a big effect thereof. Althoughthe sags can be made smaller by reducing a stock removal in the doubleside polishing step, in order to make a mirror surface a larger stockremoval is required in the subsequent secondary polishing step, andlarge sags are generated after all. Also when a wafer is subjected topolishing of the waxless system, sags are easily generated in theperiphery of the wafer as in the case of double side polishing, and theflatness level is not sufficient.

DISCLOSURE OF THE INVENTION

It is an object of the present invention to provide a wafermanufacturing method and a polishing apparatus which enable control ofsags in the periphery of the wafer that is the most difficult problem inthe polishing techniques and improvement of nanotopology values thereofthat is especially required in recent years, and also to provide wafershaving the improved quality described above.

To solve the problem described above, the wafer manufacturing methodaccording to the present invention comprises the step of performing backside polishing of the wafer to produce a reference plane thereof in apolishing process for making a mirror surface of the wafer.

The reference plane of the wafer is a plane which can be obtained byvacuum chucking a warped wafer or the like onto a flat wafer holdingplate to make forcibly the wafer flat and polishing the wafer in theflat state.

Preferably, a multistage polishing process in which a wafer is polishedin multiple stages is employed as the polishing process, and the backside polishing is performed after a primary polishing step in themultistage polishing process.

In the multistage polishing process, the wafer is preferably polished inthe sequence of double side (simultaneous) polishing, back side (singleside) polishing, front side (single side) secondary polishing, and frontside (single side) final polishing. Thus after the double sidesimultaneous polishing (primary polishing step), there is preferablyintroduced a step in which a wafer is vacuum chucked onto a flat waferholding plate to make forcibly the wafer flat and the back surfacethereof is polished.

The wafer which has been double side polished in the double sidesimultaneous polishing step is excellent in tapers, but has a problemthat sags are easily generated in its periphery; therefore in the doubleside polishing step the wafer is preferably polished with the stockremoval of the order of 5 μm to 20 μm for the both surfaces thereof.Further in the multistage polishing step the wafer is preferablypolished in the sequence of front side (single side) primary polishingbased on the front side reference polishing system, back side (singleside) polishing, front side (single side) secondary polishing, and frontside (single side) final polishing. Thus after the front side polishing(the primary polishing step) based on the front side reference polishingsystem, there is preferably introduced a step in which a wafer is vacuumchucked onto a flat wafer holding plate to make forcibly the wafer flatand the back surface thereof is polished. This is because the waferwhich has been polished according to the front side reference polishingsystem is excellent in nanotopology, but as in the double side polishingsags are easily generated in its periphery.

As an example of the polishing based on the front side referencepolishing system, there is waxless polishing based on the templatesystem or the like, and in this case it is preferable to employ such apolishing system as a wafer is held by a wafer holding portion of a softelastic film such as a backing pad or a soft film. This polishing systemcan make the front side reference polishing possible.

Next, in the back side polishing newly introduced according to thepresent invention, the wafer is preferably polished using a flat waferholding plate with a high hardness which holds the wafer by means ofvacuum chucking or the like. In this case, the wafer is preferablypolished in a manner that vacuum chucking marks are not transferred tothe wafer. For this end, the wafer should be held in a manner thatthroughholes for vacuum chucking are made smaller, or a vacuum chuckingpressure is set as low as possible. With this polishing manner, theflatness of one surface of the polished wafer is improved so as toproduce a reference plane. The stock removal in this polishing is in therange of the order of 3 to 10 μm. With this polishing manner, theflatness of the polished wafer becomes excellent up to its periphery.

It is also possible to produce a reference plane by polishing a frontsurface of the wafer, but in the present invention a reference plane isproduced by polishing a back surface thereof. That is, in the presentinvention, it is indispensable to produce a reference plane of a waferby polishing a back surface of the wafer.

This is because if the front surface is further polished after doubleside polishing or waxless polishing, sags are further generated in itsperiphery, and depending on the type of a polishing head (a waferholding method), vacuum chucking marks may be formed on the polishedsurface, so that the flatness and nanotopology of the wafer aredeteriorated.

This is also because in order to improve the nanotopology of a frontside reference, it is necessary to prevent the deterioration asdescribed above, and to adjust the flatness or peripheral sags on theback surface independent of the nanotopology of the front surface.

Although there is a technique performing the back side polishing afterthe double side polishing among the prior arts, this is not forproducing a reference plane, but for the case where the (back side)polishing is performed for intentionally making the surface roughness ofa wafer rougher to clearly discriminate between the front surface andthe back surface after the double side polishing. In the presentinvention, the polishing after the double side polishing is notperformed for making the back surface rougher, but for making the backsurface mirror polished still in this stage to improve flatness andother surface states.

It is especially preferable to perform the back side polishing after theprimary polishing. The primary polishing is performed with a double sidepolishing apparatus to remove tapers, or by waxless polishing based onthe front side reference polishing system to improve flatness of theentire wafer. After that, the back surface is polished to produce areference plane, and then the front surface is subjected to thesecondary polishing and final polishing to manufacture a wafer with noinflection point in its periphery. Now, note that the primary polishing,secondary polishing, and final (tertiary) polishing are expressed by thenumber of polishing times of a front surface of a wafer.

By introduction of the back side polishing step, flatness of the entirewafer (indirectly flatness of a front surface thereof) is improved. Tobe more precise, by vacuum chucking and polishing the front surface,when the vacuum chucking is released, the flatness and peripheral sagsof the front surface are improved without polishing the front surface.

A feature of the wafer manufacturing method according to the presentinvention resides in the point that the wafer is not vacuum chucked(fixed) when a front surface thereof is polished and the wafer is fixedwhen a back surface thereof is polished. There is no specific limitationon the fixing method of the wafer when the back surface thereof ispolished, but the wafer is fixed onto a flat wafer holding plate withadhesion by wax or vacuum chucking to make forcibly the fixed sidesurface of the wafer flat, a back surface of the wafer being polished.To be more precise, when the front surface of the wafer is polished, thewaxless polishing system based on the front side reference polishingsystem or the like is employed, and when the back surface of the waferis polished, the back side reference polishing system is employed inwhich the wafer is held on a work holding plate having a referenceplane. Especially, in that case, polishing is performed in the sequenceof the front side polishing, back side polishing, and the front sidepolishing. The front side polishing makes quality of nanotopologycompleted, and the back side polishing makes quality of flatnesscompleted. For the front side polishing after the back side polishing,the secondary polishing and final polishing should be performed, but thesame effect can be expected even when only the final polishing isperformed, or when additional polishing stages are employed in additionto the above described polishing steps. It should be noted that eitherthe front side reference polishing system or the back side referencepolishing system may be employed for polishing with a small amount ofstock removal such as final polishing.

A first aspect of the polishing apparatus according to the presentinvention comprises: a first polishing section for performing primarypolishing of a front surface of a wafer based on the front sidereference polishing system; a first inverting unit for turning the waferpolished in the first polishing section upside down; a second polishingsection for polishing a back surface of the wafer in the state where thewafer polished in the first polishing section is vacuum chucked onto aflat wafer holding plate to make forcibly the wafer flat; a secondinverting unit for turning the wafer polished in the second polishingsection upside down; a third polishing section for performing secondarypolishing of the front surface of the wafer based on the waxless system;and a fourth polishing section for performing final polishing of thefront surface of the wafer based on the waxless system.

A second aspect of the polishing apparatus according to the presentinvention including at least three polishing sections comprises: a firstpolishing section for polishing a front surface of a wafer withoutvacuum chucking a back surface of the wafer; a first inverting unit forturning the wafer polished in the first polishing section upside down; asecond polishing section for polishing the back surface of the wafer inthe state where the wafer polished in the first polishing section isvacuum chucked onto a flat wafer holding plate to make forcibly thewafer flat; a second inverting unit for turning the wafer polished inthe second polishing section upside down; a third polishing section forpolishing the front surface of the wafer without vacuum chucking theback surface of the wafer.

The wafer according to the present invention has both mirror polishedsurfaces, wherein one main surface of the wafer has a configuration thatan SFQRmax is 0.10 μm or less and there is no inflection point in acenter side of 2 mm from the peripheral edge of the wafer. Theinflection point is a point at which a configuration of the surfacechanges from a convex state to a concave state or from a concave stateto a convex state, that is, a part at which a sign of the differentialcoefficient changes from plus to minus or from minus to plus. The waferof the present invention is characterized in that there is no abruptchange in this curvature. Especially the wafer has no large change inirregularities of 0.02 μm or more. In the wafer according to the presentinvention, it is preferable that a front surface of the wafer is dividedinto a plurality of 2 mm×2 mm square areas, a PV value of each of theareas is evaluated, and the maximum PV value among the PV values for allevaluated areas is 20 nm or less.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a flow chart showing an example of a process sequence in afirst embodiment of a wafer manufacturing method according to thepresent invention, and a part (a) shows a wafer manufacturing processsequence, while a part (b) shows a polishing process sequence;

FIG. 2 is a map showing flatness of a front surface of a wafer afterhaving been polished in Inventive Example 1;

FIG. 3 is a map showing flatness of a front surface of a wafer afterhaving been polished in Comparative Example 1;

FIG. 4 is a map showing flatness of a front surface of a wafer afterhaving been polished in Comparative Example 2;

FIG. 5 is a graph showing cross-sectional shapes of peripheries ofwafers (a relationship between a distance from an edge of the wafer anda change in thickness thereof after having been polished in InventiveExample 1, Comparative Example 1, and Comparative Example 2,respectively;

FIG. 6 is a graph showing relationships between PV values and occupancyrates of wafers having been polished in Inventive Example 1, ComparativeExample 1, and Comparative Example 2, respectively;

FIG. 7 is a schematic view showing an example of a process sequence inthe first embodiment of the wafer manufacturing method according to thepresent invention;

FIG. 8 is a schematic view showing a process sequence for manufacturinga wafer in Comparative Example 1;

FIG. 9 is a schematic view showing a process sequence for manufacturinga wafer in Comparative Example 2;

FIG. 10 is a flow chart showing an example of a process sequence in asecond embodiment of the wafer manufacturing method according to thepresent invention, and a part (a) shows a wafer manufacturing processsequence, while a part (b) shows a wafer polishing process sequence;

FIG. 11 is a schematic explanatory plan view showing an embodiment of awafer manufacturing apparatus according to the present invention;

FIG. 12 is a schematic explanatory enlarged side view showing anessential part of FIG. 11;

FIG. 13 is a schematic explanatory plan view showing another embodimentof a wafer manufacturing apparatus according to the present invention;

FIG. 14 is an explanatory side view showing an example of a single sidepolishing apparatus;

FIG. 15 is a picked out cross-sectional explanatory view of an essentialpart showing an example of a double side polishing apparatus;

FIG. 16 is a picked out cross-sectional explanatory view of an essentialpart showing an example of a polishing apparatus used for back sidepolishing;

FIG. 17 is a picked out cross-sectional explanatory view of an essentialpart showing an example of a wafer polishing apparatus based on atemplate system; and

FIG. 18 is a flow chart showing an example of a process sequence of aconventional wafer manufacturing method, and a part (a) shows a wafermanufacturing process sequence, while a part (b) shows a polishingprocess sequence.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments of the present invention are described below with referenceto the appended drawings, and it is needless to say that variousmodifications are possible in addition to the embodiments withoutdeparting from the scope of the technical idea of the present invention.

FIG. 1 is a flow chart showing an example of a process sequence in afirst embodiment of a wafer manufacturing method according to thepresent invention, and a part (a) shows a wafer manufacturing processsequence, while a part (b) shows a polishing process sequence.

The wafer manufacturing process shown in FIG. 1 (a) is similar to theconventional wafer manufacturing process shown in FIG. 18 (a), but apolishing step 107 of the inventive method is different from theconventional polishing step 108.

The polishing step 107 of the inventive method, as shown in FIG. 1 (b),comprises a double side simultaneous (primary) polishing step 107 a, asingle side (backside) polishing step 107 b, a single side (front side)secondary polishing step 107 c, and a single side (front side) finalpolishing step 107 d. The different point of this process from theconventional double side polishing step 108B shown in FIG. 18 (b)resides in that the single side (back side) polishing step 107 b isprovided after the double side simultaneous (primary) polishing 107 a.As described hereinbefore, a reference plane of a wafer is produced bypolishing a back surface of the wafer; this technical point is thegreatest feature of the present invention.

To perform the double side simultaneous (primary) polishing step 107 a,there may be used the double side polishing apparatus 220 generallyknown as an apparatus polishing simultaneously both the back surface andfront surface of a semiconductor wafer as explained with reference toFIG. 15.

As for a polishing apparatus used in the back side polishing step 107 bof the inventive feature, there is no limitation as long as theapparatus can produce a reference plane, and, for instance, theapparatus as shown in FIG. 16 may be used. In FIG. 16, a wafer holdingplate 152 for polishing in a polishing apparatus 150 includes a waferholding plate body 158 which is made of hard materials such as SiC withhigh flatness and provided with a wafer holding surface 154 and a numberof throughholes 156 for vacuum chucking.

These throughholes 156 communicate through a vacuum path 160 with avacuum unit (not shown), and when a vacuum is provided therein, a wafer(W) is vacuum chucked onto the wafer holding face 154. Further the waferholding surface 154 of the wafer holding plate body 158 may be coveredwith a resin coating 162 having throughholes therein.

When polishing the wafer (W), the wafer (W) is held onto the waferholding surface 154 of the wafer holding plate for polishing use 152 bymeans of vacuum chucking or the like, and the wafer holding plate 152holding the wafer (W) is set to a polishing head 166 having a rotaryshaft 164. Then the wafer (W) is rotated by the polishing head 166 andsimultaneously is pressed to a polishing cloth adhered onto a turn table(not shown) rotating with a specified load.

The reference numeral 168 denotes an air supply path provided inparallel with the vacuum path 160, and this air supply path 168 canpress down the wafer holding plate body 158 movably supported on thewafer holding plate 152 by an elastic support portion 172 made of rubberor the like by supplying air into a pressurizing space 170 providedinside the wafer holding plate 152 and above the wafer holding platebody 158, thus the wafer (W) being pressed to the polishing cloth of theturn table (not shown) under pressure.

A polishing agent is supplied at a specified flow rate onto thepolishing cloth from a nozzle (not shown), and the wafer (W) is polishedby the use of the polishing agent supplied between the wafer (W) and thepolishing cloth. By provision of the above described polishing, areference plane of the wafer (W) can be produced.

After the above polishing, although the wafer is still flat in thevacuum chucked state, when the vacuum chucking is released, the wafer isapt to return to the original shape. At this time, peripheral sags on afront surface of the wafer are improved.

When a stock removal is large even in case of the back side polishing,sags are apt to be generated in the periphery of a wafer. However, evenif sags are generated on a back surface of a wafer, or inflection pointsare present thereon, in the secondary polishing step a front surface ofthe wafer is polished with keeping its configuration by holding a backsurface of the wafer by means of a soft backing pad or the like not totransfer a back surface configuration, whereby only the front surface ofthe wafer can be turned into a mirror surface without being affected bythe sags on the back surface thereof.

Marks of throughholes or the like may be transferred onto a polishedsurface. This is because that the wafer is forcibly vacuum chucked inthe flat state to produce a reference plane so that a strong vacuumchucking force is inevitably required, with the result thatconfigurations in the vicinity of the throughholes appear as marks afterpolishing. Such appearance of the marks of throughholes makesnanotopology of the wafer worse.

In this inventive method, however, as the back side polishing isperformed, the above mentioned vacuum chucking marks appear on the backsurface; the marks transferred onto the back surface have no effect on afront surface as in the case of the peripheral sags, so that thesecondary polishing of the front surface can be performed without anyproblems.

Therefore, it is preferable to use a polishing apparatus named CMP inthe single side (front side) secondary polishing step 107 c in theinventive method. In the CMP, a wafer is held by a soft backing pad orthe like and polished with keeping a configuration of the wafer surfaceto be polished. In this step, it is preferable to set the hardness ofthe polishing cloth to an Asker C hardness of the order of 70 to 90,that is, rather harder than the ordinary polishing cloth.

It is preferable that in this secondary polishing step 107 c, the stockremoval is 2 μm or less, and especially when both the secondarypolishing step 107 c and the final polishing step 107 d are includedtogether, the stock removal is in the order of 1 to 1.5 μm. With such astock removal level as described above, in this polishing stepgeneration of peripheral sags is prevented, and also a mirror polishedsurface is made sufficiently.

It should be noted that a configuration of a wafer can be corrected alsoin the secondary polishing step 107 c by increasing the stock removalwith a polishing head using a retainer ring or the like. However, whensuch polishing as described above is performed, a wafer havinginflection points may be easily manufactured. Therefore, in thesecondary polishing step 107 c, it is preferable to set a stock removalin a manner that correction of a configuration of a wafer issubstantially not made, and to polish the wafer with keeping theconfiguration obtained in the primary polishing step 107 a (and backside polishing step 107 b).

In the final polishing step 107 d, polishing is performed using theconventional single side polishing apparatus 200 as described in FIG. 14and a suede type polishing cloth and the like.

Generally, there is a tendency that the more stock removal, the largerperipheral sags of a wafer. Therefore, in order to improve flatness andnanotopology of a reference plane, a stock removal of the front surfaceof the wafer should be desirably small.

By improving flatness (peripheral sags) in the state where a stockremoval of the entire front surface of a wafer is small and polishingthe wafer in a manner that a back surface of the wafer is nottransferred in the secondary polishing step and afterward, it ispossible to manufacture a wafer having improved flatness andnanotopology for the surface reference, and especially a wafer having nochange in irregularities of 0.02 μm or more, that is, no largeinflection point in the vicinity of 2 to 20 mm from a peripheral edge ofthe wafer.

Next, using FIG. 7 that is a schematic view showing an example of aprocess sequence in the first embodiment of the wafer manufacturingmethod according to the present invention, there are explained changesin a configuration of a wafer in each of the polishing steps in theinventive process. At first, a front surface (A) and a back surface (B)of a wafer (W) are subjected to the primary (double side) polishing, forinstance, by the use of the same double side polishing apparatus asshown in FIG. 1 (FIG. 7 (a)).

The polishing conditions for this primary (double side) polishing stepare not limited especially but the polishing should preferably beperformed under the following conditions.

Polishing load: 200 to 600 g/cm² (20 to 60 kPa)Polishing cloth: nonwoven fabric type (an Asker C hardness of the orderof 60 to 80)Polishing agent: containing colloidal silica (pH 10 to 11)Supplying rate: 4 to 6 L/minStock removal: in the order of 5 μm to 20 μm for both surfaces, and morepreferably about 16 μm for both surfaces.

The above Asker C hardness is a value measured using an Asker rubberhardness meter Model C that is one of spring hardness testers, andcorresponds to SRIS 0101 that is the Society of Rubber Industry (Japan)Standard.

This wafer (W) polished in the double side polishing step is improved intapers, but sags (E) have been generated in the periphery of the wafer(W) as shown in FIG. 7 (a).

Then this wafer (W) is subjected to the back side polishing (productionof a reference plane) (FIG. 7 (b), (c) and (d)). In this back sidepolishing step, as a polished wafer holding plate for the polishingapparatus, there is used a hard holding plate 152 made of SiC whichincludes the wafer holding surface 154 and a number of throughholes 156for vacuum chucking and the holding surface 154 of the wafer holdingplate 152 is covered with an epoxy resin coating film 162 as thepolishing apparatus 150 shown in FIG. 16.

When vacuum chucking the wafer (W) with this wafer holding plate 152,the vacuum chucked wafer surface becomes flat with irregularities beinggenerated on the other wafer surface. FIG. 7 (b) shows the state wherethe bottom surface of the wafer becomes convex, In this state the sags(E) in the periphery section of the wafer (W) increase by a factor oftwo (E×2).

When polishing this wafer in a vacuum chucked state, a flat wafer (W) ismanufactured as shown in FIG. 7 (c).

The polishing conditions for this back side polishing step are notlimited especially but the polishing should be preferably performedunder the following conditions.

Polishing load: 200 to 600 g/cm² (20 to 60 kPa)Polishing cloth: nonwoven fabric type (an Asker C hardness of the orderof 60 to 80)Polishing agent: containing colloidal silica (pH 10 to 11)Supplying rate: 5 to 15 L/minStock removal: in the order of 3 μm to 8 μm and more preferably about 5μm.

By the provision of the back side polishing step as described above, areference plane of the wafer can be produced. However, even in thispolishing, sags may be slightly generated in the periphery of the wafer.Although the wafer is flat in the vacuum chucked state, when the vacuumchucking is released, the wafer is apt to return to the originalconfiguration as shown in FIG. 7 (d). Also as shown in FIG. 7 (d), thevacuum chucking marks (D) may be transferred onto the polished surface.The sags (e) or vacuum chucking marks (D) appear only on the backsurface (B) of the wafer (W), and although the front surface (A) of thewafer (W) is improved in flatness, the surface state thereof isunchanged as compared with that subjected to the primary polishing.

The wafer (W) in the state described above is subjected to the secondary(front side) polishing (FIG. 7 (e) and (f)). Any type of polishingapparatus and polishing method conventionally employed may be applied tothe secondary polishing without any special limitation, but there ispreferably used for the above polishing the polishing apparatus 240 asshown in FIG. 17 wherein a wafer is held by the backing pad 250 and apolishing cloth slightly harder than that used in the conventionalsecondary polishing step is used.

The polishing conditions for this secondary (front side) polishing stepare not limited especially but the polishing should be preferablyperformed under the following conditions.

Polishing load: 100 to 300 g/cm² (10 to 30 kPa)Polishing cloth: nonwoven fabric type, suede type or polyurethane type(anAsker C hardness of the order of 70 to 90)Polishing agent: containing colloidal silica (pH=10 to 11)Supplying rate: 10 L/min or moreStock removal: several μm, preferably 2 μm or less.

Briefly, in the secondary (front side) polishing step, using CMP withthe soft backing pad 250 (FIG. 17) and the relatively hard polishingcloth, a wafer is polished in a manner that only a configuration of thefront surface of the wafer is corrected without a configuration of theback surface thereof being transferred. The backing pad 250 (FIG. 17) ispreferably made of a urethane foam pad and is 300 μm or less inthickness. The hardness of the polishing cloth should be preferably inthe Asker C hardness of the order of 70 to 90.

There is no specific limitation on the polishing cloth used in each ofthe polishing steps, but as a polishing cloth (or polishing pad) in thepolishing steps a nonwoven type polishing cloth or a suede typepolishing cloth is mainly used.

The nonwoven type polishing cloth is generally made of polyester felt(its tissue has random structure) impregnated with polyurethane, and hasporosity, adequate elasticity, and excellence in a high polishing rateand flatness, thereby being capable of making the stock removal large,which is used mainly in the primary or secondary polishing step orothers.

The suede type polishing cloth is generally composed of a base body madeof polyester felt impregnated with polyurethane, a foamed layer formedin the polyurethane and opening portions provided on the formed layer byremoving the surface section of the polyurethane (this layer is named anap layer), and is used especially for finishing, a polishing agent keptin the foamed layer being reacted between a work and an internal surfaceof the foamed layer to let the polishing proceed. This suede typepolishing cloth is used very often in chemical mechanical polishing togive a surface of no damage.

Recently, there has been developed a three layer polishing cloth notusing nonwoven fabrics which comprises, for instance, a base body of ahard plastic sheet, a surface layer of a nap layer made of urethane, andan elastic sheet provided under the base body. Among the polishingcloths described above the most suitable one to each of the polishingsteps should be selected. Further a step similar to this secondarypolishing step may be provided additionally.

The wafer (W) polished in the secondary polishing is subjected to thefinal polishing (FIG. 7 (g)). The final polishing may be performed usinga conventional method. The polishing apparatus for the final polishingis not limited especially and the final polishing step should bepreferably performed under the following conditions.

Polishing load: 100 to 200 g/cm² (10 to 20 kPa)Polishing cloth: suede typePolishing agent: containing colloidal silica (pH 10 to 11)Supplying rate: 0.5 to 1 L/minStock removal: A stock removal of 0.1 μm or less is enough.

In the wafer which has been polished through the polishing steps asshown in FIG. 7 (a) to FIG. 7 (g), there are few inflection points andthe like on the surface thereof and the sags are improved; a wafer withhigh flatness can be manufactured. Polishing conditions in each stepabove described may be appropriately determined to the most suitableconditions according to a configuration of a wafer.

In the first embodiment of the inventive method shown in FIG. 1, thereis described the case where the double side simultaneous polishing isperformed as the primary polishing, but another type polishing methodmay be used as the primary polishing, and this method is describedbelow. FIG. 10 is a flow chart showing an example of a process sequencein a second embodiment of the wafer manufacturing method according tothe present invention, and a part (a) shows a wafer manufacturingprocess sequence, while a part (b) shows a wafer polishing process.

The wafer manufacturing process shown in FIG. 10 (a) is the same as theconventional wafer manufacturing process shown in FIG. 18 (a) and thefirst embodiment of the inventive wafer manufacturing process shown inFIG. 1( a), but a polishing step 307 in the second embodiment isdifferent from the conventional polishing step 108 and the polishingstep 107 shown in FIG. 1 (a).

The polishing step 307 of the second embodiment according to theinventive method, as shown in FIG. 10 (b), comprises a front side(single side) primary polishing step 307 a based on the front sidereference polishing system, a back side (single side) polishing step 307b, a front side (single side) secondary polishing step 307 c, and afront side (single side) final polishing step 307 d. The front side(single side) primary polishing step 307 a based on the front sidereference polishing system means polishing for one based on theso-called template system using a backing film or the waxless systemincluding a polishing system holding a wafer by an elastic body andother polishing systems. That is, it is a polishing system in which awafer is polished in a manner that the wafer is not forcibly held bymeans of vacuum chucking or the like, and is not fixed to a holdingplate or the like to be a reference plane. The different point of thissystem from the conventional waxless polishing step 101A shown in FIG.18 (b) resides in that the single side (back side) polishing 307 b isperformed after the waxless polishing step 307 a based on the front sidereference polishing system. As described above, the greatest feature ofthis invention is in that a reference plane of a wafer is produced bypolishing a back surface of the wafer.

To carry out the polishing step 307 a based on the front side referencepolishing system, the polishing apparatus as already described withreference to FIG. 17 may be used.

The back side polishing step 307 b, secondary polishing step 307 c, andfinal polishing step 307 d correspond to the back side polishing step107 b, secondary polishing step 107 c, and final polishing step 107 dshown in FIG. 1 (b), respectively, and these steps are equal to eachother, so a repetitious description thereof is omitted.

Changes in a configuration of a wafer in each of the polishing steps inthe second embodiment of the inventive process are almost similar to thedescription of FIG. 7 showing the first embodiment of the presentinvention. A different point of the second embodiment from the firstembodiment resides in that a wafer after the polishing step 307 a basedon the front side reference polishing system has a surface state wherethe front surface thereof turns into a mirror surface and the backsurface thereof is an etched surface. However, sags are generated in theperiphery of the wafer (W) due to polishing as well as etching, and theconfiguration thereof is similar to that shown in FIG. 7 (a).

The second embodiment of the inventive method is described belowfocusing on the different point thereof from the first embodiment of theinventive method in which double side polishing is performed in theprimary polishing step. The polishing conditions for the polishing(primary polishing) step based on the front side reference polishingsystem in the second embodiment of the inventive method are not limitedespecially but the polishing should be preferably performed under thefollowing conditions.

Polishing load: 200 to 600 g/cm² (20 to 60 kPa)Polishing cloth: unwoven fabric type (an Asker C hardness of the orderof 60 to 80)Polishing agent: containing colloidal silica (pH=10 to 11)Supplying rate of polishing agent: 4 to 6 L/minStock removal: 5 to 10 μm, preferably about 8 μm.

Then this wafer is subjected to the back side polishing. That is, areference plane is produced corresponding to FIGS. 7 (b), 7 (c), and 7(d). When the primary polishing step is, for instance, waxless polishingbased on the template system, the sags in the periphery of the wafershown in FIG. 7 (b) are the sum of the sags on the front surface(polished surface) and the sags on the back surface (etched surface).

The polishing conditions for the back side polishing step in the secondembodiment of the inventive method are not limited especially but thepolishing should be preferably performed under the following conditions.

Polishing load: 200 to 600 g/cm² (20 to 60 kPa)Polishing cloth: unwoven fabric type (an Asker C hardness of the orderof 60 to 80)Polishing agent: containing colloidal silica (pH 10 to 11)Supplying rate of polishing agent: 5 to 15 L/minStock removal: 5 to 10 μm, preferably about 8 μm.

As the back surface of the wafer is an etched surface, in the primarypolishing step the wafer is preferably polished with the stock removalbeing slightly larger than that when the double side polishing isperformed. The subsequence steps are equal to those in the firstembodiment of the inventive method shown in FIG. 1 (b), so a repetitiousdescription thereof is omitted.

The multistage polishing in the second embodiment of the inventivemethod may be performed using independent polishing apparatuses such asan apparatus specialized for performing the primary polishing step, andan apparatus specialized for performing the back side polishing step,but it is preferable to use a composite polishing apparatus in which aplurality of polishing apparatuses are integrally arranged. FIG. 11 is aschematic explanatory plan view showing an embodiment of the inventivecomposite polishing apparatus suited for performing the secondembodiment of the inventive method in which four independent polishingapparatuses are integrally arranged.

In FIG. 11, a polishing apparatus 400 according to the present inventioncomprises four different types of polishing apparatuses arrangedsuccessively; a frontside (single side) primary polishing section (afirst polishing section) 401, a back side (single side) polishingsection (a second polishing section) 402, a front side (single side)secondary polishing section (a third polishing section) 403, and a frontside (single side) final polishing section (a fourth polishing section)404.

In FIG. 11, reference numeral 405 denotes a first conveyor arm forconveying a wafer from a previous step to the first polishing section401. A first inverting unit 406 for turning a wafer upside down isprovided between the first polishing section 401 and the secondpolishing section 402, whereby a wafer with the polished front surfacecan be turned over for polishing the back surface thereof in the nextstep. Similarly, a second inverting unit 407 for turning a wafer upsidedown is provided too between the second polishing section 402 and thethird polishing section 403, and hence the front surface of the wafercan be polished in the third polishing section 403.

The mechanism for turning over a wafer as described above is notrequired in the conventional polishing apparatus in which only a frontsurface of a wafer is polished, but in the present invention, it isimportant to perform polishing in the sequence of front side polishing,back side polishing, and front side polishing; therefore the mechanismas described above is required. In FIG. 11, reference numeral 408denotes a second conveyor arm, which conveys a wafer polished in thethird polishing section 403 to the fourth polishing section 404.Designated by 409 is a third conveyor arm, which conveys a wafer finalpolished in the fourth polishing section 404 to the next step.

FIG. 12 is a schematic explanatory side view showing the first polishingsection 401. In this figure, designated by 410 is a base, and a turntable 411 is provided on a top surface thereof. This turn table 411 isrotatably driven by a drive shaft (not shown). The polishing cloth 412is adhered on a top surface of the turn table 411, and polishing isperformed supplying slurry 414 from the slurry supplying unit 413 ontothis polishing cloth 412. A polishing head 415 is hung movably up anddown and rotatably, and a wafer held thereby is polished by pressing itslidably onto the polishing cloth 412 at an optional polishing pressure.Further each polishing section may comprise a polishing apparatus basedon a batch system in which a plurality of wafers are processed together,but it is preferable to use a polishing apparatus having a single waferpolishing head 415 which processes wafers sheet by sheet because adiameter of a wafer becomes larger and this type of polishing apparatusis easy to handle. Here, the polishing head 415 may be based on either asingle shaft system or a multiple shaft system (the so-calledmulti-shaft single wafer system). It should be noted that the basicstructure of the first polishing section 401 is common to the secondpolishing section 402, third polishing section 403, and fourth polishingsection 404 excluding the different points in the concrete structure ofthe polishing head 415 as described below, and individual description ofeach of the polishing sections 402 to 404 is omitted.

The polishing head (246 in FIG. 17) based on the waxless system as shownin FIG. 17 is used as a polishing head 415 of the first polishingsection 401 shown in FIG. 12. In the second polishing section 402, thepolishing head (166 in FIG. 16) having a polishing mechanism based onthe vacuum chucking system as shown in FIG. 16 is used as a polishinghead, and thereby a wafer is vacuum chucked onto a flat wafer holdingplate (152 in FIG. 6) for making forcibly the wafer flat and polishingthe back surface thereof. The polishing head (246 in FIG. 17) based onthe waxless system as shown in FIG. 17 is used as a polishing head inthe third polishing section 403 and in the fourth polishing section 404.It is preferable to perform polishing for the front surface under theconditions enabling gradually fine polishing as the polishing proceeds.Especially the polishing in each step should be performed under thepolishing conditions as described above.

The operation of the polishing apparatus 400 according to the presentinvention will now be described. At first, an etched wafer is conveyedto the first polishing section 401 by the first conveyor arm 405. Thefirst polishing section 401 is provided with a polishing head (246 inFIG. 17) based on the waxless system as shown in FIG. 17 as thepolishing head 415, and holds a back surface of a wafer for polishing asurface (front surface) for fabricating a device thereon. Then, thepolishing head 415 is moved downward and performs polishing underoptional polishing conditions (the primary polishing conditions).

The polished wafer is turned upside down by the first inverting unit406. There is no specific limitation on the inverting function of thewafer inverting unit 406, but a wafer may be preferably turned upsidedown by a robot arm or the like.

The inverted wafer with the back surface now faced upward is thenconveyed to the second polishing section 402, and the front surface ofthe wafer is held by a polishing head similar to the polishing head (166in FIG. 16) as shown in FIG. 16, thereby the wafer being forcibly flat,and after that the polishing head is moved down to polish the backsurface of the wafer under optional polishing conditions (the backsurface polishing conditions).

The polished wafer is again turned upside down by the second invertingunit 407 having the same inverting function as the first inverting unit406.

The wafer again turned upside down with the front surface faced upwardnow is then conveyed to the third polishing section 403, and the backsurface of the wafer is held by a polishing head as shown in FIG. 17,and after that the polishing head is moved down to secondary polish thefront surface of the wafer under optional polishing conditions (thesecondary polishing conditions).

Next, the secondary polished wafer is conveyed to the fourth polishingsection 404 by the second conveyor arm 408, and the back surface of thewafer is held by a polishing head (246 in FIG. 17) as shown in FIG. 17,and after that the polishing head is moved down to final polish thefront surface of the wafer under optional polishing conditions (thefinal polishing conditions).

After the final polishing, the wafer is conveyed to the subsequentcleaning process by the third conveyor arm 409.

With the process sequence as described above, the front surface and backsurface of the wafer are polished to thereby obtain a wafer with highflatness.

The embodiment shown in FIG. 11 shows an example in which four polishingapparatuses are integrally arranged to form the polishing apparatusaccording to the present invention, but the polishing apparatusaccording to the present invention can also be formed by arranging threepolishing apparatuses integrally. FIG. 13 is a schematic explanatoryplan view showing another embodiment of a polishing apparatus accordingto the present invention in which three polishing apparatuses areintegrally arranged.

In FIG. 13, a polishing apparatus 500 according to the present inventioncomprises three different types of polishing apparatuses arrangedsuccessively; a front side (single side) primary polishing section (afirst polishing section) 502, a back side (single side) polishingsection (a second polishing section) 503, and a front side secondaryfinal polishing section (third polishing section) 504. Designated by 501is a loader section comprising a first delivery stage 501 a and a firstconveyor arm 506. Designated by 505 is an unloader section comprising afifth delivery stage 505 a.

The first polishing section 502 comprises first and second polishingstages 507, 508, a first positioning stage 509, second and thirdconveyor arms 510, 511, and a second delivery stage 512. The first andsecond polishing stages 507, 508 are provided with first and secondheads 507 a, 508 a, and first and second polishing machine loaders 507b, 508 b, respectively.

The second polishing section 503 comprises third and fourth stages 513,514, a second positioning stage 515, fourth and fifth conveyor arms 516,517, a third delivery stage 518, and further a first cleaning unit 519.The fourth conveyor arm 516 functions as a first inverting unit. Thethird and fourth polishing stages 513, 514 are provided with third andfourth polishing heads 513 a, 514 a and third and fourth polishingmachine loaders 513 b, 514 b.

The third polishing section 504 comprises fifth and sixth polishingstages 520, 521, a third positioning stage 522, sixth and seventhconveyor arms 523, 524, a fourth delivery stage 525, and further asecond cleaning unit 526. The sixth conveyor arm 523 functions as asecond inverting unit. The fifth and sixth stages 520, 521 are providedwith fifth and sixth heads 520 a, 521 a, and fifth and sixth polishingmachine loaders 520 b, 521 b, respectively. In the example shown in FIG.13, among the two polishing stages, namely the fifth and sixth polishingstages 520, 521 in the third polishing section 504, the fifth polishingstage 520 is used for front side secondary polishing, and the sixthpolishing stage 521 is used for final polishing.

With the construction described above, the operation will now bedescribed. At first, wafers to be polished are supplied from the loader501. The wafers are conveyed by the first conveyor arm 506 from thefirst delivery stage 501 a to the first positioning stage 509, where thewafers are positioned, and the wafers are conveyed and set by the secondconveyor arm 510 to the first and second polishing loaders 507 b, 508 b.Then, the wafers are conveyed to the undersides of the first and secondpolishing heads 507 a, 508 a in the first polishing section (front sideprimary polishing section) 502 by the first and second polishing machineloaders 507 b, 508 b, and the wafers are held by the first and secondpolishing heads 507 a, 508 a. After that, the first and second polishingmachine loaders 507 a, 508 b are returned to the original positions. Thewafers held by the first and second polishing heads 507 a, 508 a arepressed slidably on the polishing cloth and polished thereby. In theexample shown in FIG. 13, in order to improve the work efficiency, twopolishing stages, namely the first and second polishing stages 507, 508are provided, and wafers are supplied to the polishing stages andpolished therein, respectively. The wafers polished therein are againconveyed to outside of the polishing machine by the first and secondpolishing machine loaders 507 b, 508 b, and are conveyed to the seconddelivery stage 512 by the second conveyor arm 510.

Next, the front side primary polished wafers are conveyed by the thirdconveyor arm 511 to the first cleaning unit 519 of the second polishingsection 503 where the wafers are cleaned. This cleaning unit 519 shouldbe preferably based on dipping type cleaning by the use of a SC1 liquid(a cleaning liquid mixture of ammonia, hydrogen peroxide and water), inwhich a wafer is processed in the sequence of a rinsing liquid, the SC1liquid, a rinsing liquid, and a rinsing liquid.

After this cleaning, the wafers are turned upside down by the fourthconveyor arm (the first inverting unit) 516 and are conveyed to thesecond positioning stage 515 where the wafers are positioned. Thepositioned wafers are conveyed by the fourth conveyor arm 516 to thethird and fourth polishing machine loaders 513 b, 514 b. Then the wafersare conveyed by the third and fourth polishing machine loaders 513 b,514 b to undersides of the polishing heads 513 a, 514 a in the secondpolishing section (back side polishing section) 503, and the backsurfaces of the wafers are polished in the state where the wafers areheld by the polishing heads 513 a, 514 a. In the example shown in FIG.13, two polishing stages, namely third and fourth polishing stages 513,514 are provided for improving the work efficiency, and wafers aresupplied to the respective polishing stages where the wafers arepolished. The wafers polished therein are conveyed by the third andfourth polishing machine loaders 513 b, 514 b to outside of thepolishing machines and are conveyed by the fourth conveyor arm 516 tothe third delivery stage 518. This back side polished wafers areconveyed by the fifth conveyor arm 517 to the second cleaning unit 526in the third polishing section 504 (its cleaning conditions are the sameas those of the first cleaning unit 519) for cleaning.

After the cleaning, the wafers are turned upside down by the sixthconveyor arm (the second inverting unit) 523, and are conveyed to thethird positioning state 522 for positioning. The positioned wafers areconveyed to the fifth and sixth polishing loaders 520 b, 521 b by thesixth conveyor arm 523. After that, the wafers are conveyed by the fifthand sixth polishing machine loaders 520 b, 521 b to the fifth polishingstage (front side secondary polishing stage) 520 in the third polishingsection (front side secondary polishing/final polishing section) 504,where front surfaces of the wafers are secondary polished. The frontside secondary polished wafers are conveyed by the fifth polishingmachine loader 520 b to outside of the polishing machine, and arepositioned by the sixth conveyor arm 523 at the third positioning stage522, and then are conveyed again by the sixth conveyor arm 523 to thesixth polishing machine loader 521 b. Next, the wafers are conveyed bythe sixth polishing machine loader 521 b to the final polishing stage(the sixth polishing stage) 521 in the third polishing section 504 wherethe wafers are final polished.

The final polished wafers are conveyed by the sixth polishing machineloader 521 b to outside of the polishing machine and are conveyed by thesixth conveyor arm 523 to the fourth delivery stage 525. This finalpolished wafers are conveyed by the seventh conveyor arm 524 to thefifth delivery stage 505 a in the unloader section 505, and finally areconveyed to the next (cleaning) step.

EXAMPLES

The present invention will be more specifically described with referenceto examples thereof, but it is needless to say that these examples arenot construed to limit the scope of the invention.

Inventive Example 1

An 8-inch wafer having been subjected to a general process includingslicing, chamfering, lapping, and etching was polished by the inventivemethod.

The polishing process in the inventive method was carried out, as shownin FIG. 7) in the sequence of a double side (simultaneous) polishing(front side primary polishing) step (FIG. 7 (a)),→a single sidepolishing (back side polishing) step (FIGS. 7 (b), 7 (c), and 7 (d)),→asingle side secondary polishing (front side secondary polishing) step(FIGS. 7 (e), and 7 (f)),→a single side final polishing (front sidetertiary polishing) step (FIG. 7 (g)).

(1) Double Side (Simultaneous) Primary Polishing Step

The AC 2000 (made by Peter Wolters AG) was used as a double sidepolishing apparatus. The polishing conditions were as described below.

Polishing load: 300 g/cm² (30 kPa)Polishing cloth: SUBA 600 (a trade name of Rodel Nitta Company) (anAsker C hardness of 78)Polishing agent: HP-20 (a trade name of Fujimi Incorporated) (pH 10.5)Supplying rate: 5 L/minStock removal: polished with 8 μm for one surface (16 μm for twosurfaces).

(2) Single Side (Back Side) Polishing Step

The FSP-200 (made by Fujikoshi Machinery Corp.) was used as a polishingapparatus. The polishing conditions were as described below. A waferholding plate made of SiC ceramics having high flatness and coated withepoxy resin was used.

Polishing load: 300 g/cm² (30 kPa)Polishing cloth: SUBA 600 (a trade name of Rodel Nitta Company) (anAsker C hardness of 78)Polishing agent: AJ-1325 (a trade name of Nissan Chemical Industries,Ltd.) (pH=10.5)Supplying rate: 10 L/minStock removal: polished with 5 μm.

(3) Single Side (Front Side) Secondary Polishing Step

The FSP-200 (made by Fujikoshi Machinery Corp.) was used as a polishingapparatus, and the polishing conditions were as described below. Aurethane foam pad was used as a backing pad for holding a wafer.

Polishing load: 200 g/cm² (20 kPa)Polishing cloth: PU pad (a trade name of Rodel Nitta Company) (an AskerC hardness of 80)Polishing agent: SSS (a trade name of Nissan Chemical Industries, Ltd.)(pH 10.5)Supplying rate: 10 L/minStock removal: about 1 μm.

(4) Final Polishing Step

The FSP-200 (made by Fujikoshi Machinery Corp.) was used as a polishingapparatus, and the polishing conditions were as described below.

Polishing load: 150 g/cm² (16 kPa)Polishing cloth: FS-7 (a trade name of Daiichi Lace Inc.)Polishing agent: Fujimi 3900 (a trade name of Fujimi Incorporated)Supplying rate: 500 mL/minStock removal: 0.1 μm or less.

Evaluation for flatness and nanotopology of the wafer having beensubjected to the polishing steps described above was carried out. FIG. 2is a map showing flatness of the polished wafer. This map was obtainedby measuring with a thickness measurement apparatus having a capacitivesensor (7900E+Station made by ADE Corp.). The flatness (SFQRmax) of thiswafer was 0.071 μm, which was very excellent.

FIG. 5 shows a cross-sectional shape of the periphery of the wafer. Withedge exclusion of 2 mm, and a position of 2 mm from the peripheral edgeis shown as the reference (zero) therein. The polished wafer hadexcellent quality that the peripheral sags were improved and also noinflection point was observed.

Further the nanotopology was evaluated as shown in FIG. 6. Thisevaluation is based on such a manner that a wafer was divided to aplurality of areas (areas each 2 mm square), irregularities of eachsquare were confirmed, what percent of the wafer the areas having avalue for the irregularities (a PM value) occupy (occupancy rate) waschecked, and the checked PV values were accumulated in a sequence offrom a larger value to a smaller one. The nanotopology was evaluatedwith WIS CR83-SQM made by ADE Corp.

According to the graph showing the results in Inventive Example 1, thearea with the PV value of 18.0 nm is almost zero, and this indicatesthat irregularities larger than the PV value are not present in case ofthe nanotopology observed on the basis of the 2 mm square area.

To be more precise, in evaluation of nanotopology, an irregularityheight, at which the occupancy rate becomes zero %, (an area indicatingthe largest PV value) is important. In this example, the largest PMvalue is 18.0 nm, and this small value shows that the wafer surfaceincludes very few irregularities (a wafer surface having excellentnanotopology).

Comparative Example 1

A wafer similar to that used in Example 1 was subjected to the polishingprocess shown in FIG. 8, that is, the process comprising a double side(front side primary) polishing step (FIG. 8 (a); the peripheral sags (E)of the wafer are large),→a single side secondary (front side secondary)polishing step (FIG. 8 (e) and 8 (f); the peripheral sags (E) of thewafer become large with the flatness being not very much improved,(inflection points may be produced when a retainer ring or the like isused)),→a single side final (front side tertiary) polishing step (FIG. 8(g); the flatness in the periphery of a wafer is not very muchimproved). The polishing process was performed under the same conditionsas those employed in Example 1 excluding the single side (back side)polishing.

After the double side polishing (FIG. 8 (a)) was finished (in the stageof primary polishing), the flatness (SFQRmax) of the wafer was about0.126 μm. The flatness was kept unchanged also after the secondarypolishing was finished, and the wafer configuration was little correctedin the secondary polishing step. Rather peripheral sags were slightlygenerated in the secondary polishing step.

A configuration of a wafer having been subjected to the polishing stepsas described above is shown in FIG. 3. There has known therefrom thefact that contour lines are crowded in the periphery of the wafer, whichindicates that there are sags in the crowded portion. There is knownalso from FIG. 5 the fact that the wafer configuration sharply changesin thickness of the periphery from the points of about 6 mm from thewafer edge. In short, it is a problem with the above described polishingthat the flatness (especially the flatness in the periphery) of thewafer cannot be improved.

The nanotopology is shown in FIG. 6, and as shown in the graph ofComparative Example 1, the irregularity height for the occupancy rate of0% is in the range from 30 to 40 nm, which indicates that relativelylarge irregularities were present on the wafer surface (wafer surfacewith poor nanotopology).

Comparative Example 2

A wafer similar to that used in Example 1 was subjected to the polishingprocess shown in FIG. 9, that is, the process comprising a double side(front side primary) polishing step (FIG. 9 (a); peripheral sags (E) ofthe wafer are large),→single side (front side secondary) polishing step(FIG. 9 (b); the state where the wafer is vacuum chucked (beforepolishing), FIG. 9 (c); the state where the wafer is vacuum chuckedafter polishing, FIG. 9 (d); the state after the wafer is released fromthe vacuum chucked state (the flatness of the wafer is improved, butvacuum chucking marks (D) or inflection points (M) may be generated onthe surface (A)),→a single side secondary (front side tertiary)polishing step (FIG. 9 (e); a front surface (A) of the wafer is polished(in the state where the configuration is maintained), FIG. 9 (f)),→asingle side final (front side quaternary) polishing step (FIG. 9 (g);the wafer has the inflection points (M) or vacuum chucking marks (D) onthe front surface thereof, and the flatness and nanotopology of thefront side reference are deteriorated). In brief, in this ComparativeExample, in stead of the back side polishing step in Inventive Example1, a front surface of the wafer was polished. On the same conditions asthe back side polishing step in Inventive Example 1, a reference planewas produced on a surface (front surface) contrary to that in InventiveExample 1. Other conditions were the same as in Inventive Example 1.

The flatness of the wafer was improved to about 0.110 μm in terms ofSFQRmax, but the improvement was not sufficient. When inspected with amagic mirror, there were some cases where marks of the throughholes wereobserved on the polished surface, and further the nanotopology(irregularity height for occupancy rate of 0%) was about 25 nm,

A configuration of the wafer (map) was as shown in FIG. 4. There wassometimes observed the wafer configuration like an inflection point wasobserved at a point about 6 mm from the peripheral edge thereof as shownin FIG. 5. In other words, although the flatness was improved,improvement of the nanotopology was not sufficient,

Data for the flatness (SFQR) in Inventive Example 1, Comparative Example1, and Comparative Example 2 are shown in Table 1. SFQR for each cellwithin the wafer surface is 0.04 μm in all of Inventive Example 1 andComparative Examples 1 and 2 (the value in Inventive Example 1 is alittle better), but comparing the maximum value thereof, the value inInventive Example 1 is clearly better. The evaluation was performed forcells each having a size of 25 mm×25 mm (25 mm square).

Also variations (d) among the cells were improved, which indicates thata wafer not having inflection points or the like is manufactured. Incases of 3 mm exclusion and 2 mm exclusion, the values of theComparative Examples deteriorate largely as compared to those of theInventive Example. This shows in the Comparative Examples that thecloser to the periphery, the larger the sags.

TABLE 1 SFQR (3 mm exclusion) SFQR (2 mm exclusion) Average Averagevalue σ Max value σ Max Inventive 0.037 0.010 0.071 0.039 0.012 0.092Example 1 Comparative 0.044 0.024 0.131 0.048 0.030 0.155 Example 1Comparative 0.037 0.013 0.110 0.043 0.023 0.118 Example 2

In Table 1, 3 mm exclusion means that a portion up to 3 mm from an edgeof a wafer (a wafer peripheral edge) is not evaluated when the waferflatness is evaluated, and the above value was obtained by evaluatingthe areas inner from the above portion. Likewise, 2 mm exclusion meansthat the portion up to 2 mm from the edge of the wafer (the waferperipheral edge) is not evaluated.

In the methods employed in the Comparative Examples, SFQRmax values wereat best in the range from 0.10 to 0.15 μm, and SBIRmax values wereimproved only up to 0.3 μm, which are not shown herein, but by addingthe back side polishing as in the Inventive Example, it is possible tostably manufacture wafers with SFQRmax of 0.10 μm or less and theSBIRmax of 0.3 μm or less. Further wafers having excellent nanotopologycan be manufactured easily.

Inventive Example 2

A wafer similar to that used in Inventive Example 1 was polished as inInventive Example 1 excluding the point that polishing based on thewaxless system using a template was performed in place of the doubleside (front side primary) polishing. To be more precise, the wafer wassubjected to a polishing process comprising a front side (single side)primary polishing step based on the front side reference polishingsystem,→a back side (single side) polishing step,→a front side (singleside) secondary polishing step,→a front side (single side) finalpolishing step.

In Inventive Example 2, a polishing apparatus capable of successivelyperforming front side (single side) primary polishing based on the frontside reference polishing system, back side polishing, front sidesecondary polishing, and final polishing was used. More specifically,there was used a polishing apparatus, in which three polishing machines(three polishing sections) as shown in FIG. 13 are arranged integrallywith two polishing stages being provided in each polishing section.

In each cleaning unit, there was employed a cleaning system in whichusing a dipping type cleaning with a SC1 liquid (a cleaning liquidmixture of ammonia, hydrogen peroxide and water), a wafer was treated inthe sequence of the rinsing liquid, SC1 liquid, rinsing liquid, andrinsing liquid.

Polishing conditions in each polishing section in Inventive Example 2were as those in Inventive Example 1 in terms of the polishing load,polishing cloth, polishing agent, supplying rate of the polishing agent,and stock removal, excluding the polishing conditions of the front side(single side) primary polishing step based on the front side referencepolishing system and 8 μm of the stock removal in the back sidepolishing. The front side (single side) primary polishing based on thefront side reference polishing system is waxless polishing based on thetemplate system in which a urethane foam pad was used as a backing padfor holding a wafer. The polishing conditions were as described below:

Polishing load: 300 g/cm² (30 kPa)Polishing cloth: SUBA 600 (a trade name of Rodel Nitta Company) (anAsker C hardness of 78)Polishing agent: HP-20 (a trade name of Fujimi Incorporated) (pH=10.5)Supplying rate: 5 L/minStock removal: 10 μm

With the polishing apparatus and the polishing conditions as describedabove, the wafer was polished, and the result of the polishing showedthat the flatness of the polished wafer (SFQRmax; 2 mm exclusion) was0.10 μm. Further the irregularity height for the occupancy rate of 0% inthe evaluation of nanotopology was 20 nm, which was very excellent. TheSBIRmax was 0.14 μm, which was also excellent.

CAPABILITY OF EXPLOITATION IN INDUSTRY

As described above, according to the present invention, it is possibleto perform control of sags in the periphery of the wafer that is themost difficult problem in the polishing techniques, and to manufacture awafer with excellent flatness including the portion of 2 mm or less fromthe wafer edge, especially a wafer having no inflection point inflatness in an inner portion from 3 mm of the wafer periphery, andfurther a wafer with excellent nanotopology especially required inrecent years, that is, a wafer with excellent flatness and nanotopology.

1-11. (canceled)
 12. A wafer with at least one mirror polished surface,wherein one main surface of the wafer has a configuration that anSFQRmax is 0.10 μm or less, wherein said wafer has no inflection pointfrom the central portion of the wafer to 2 mm from the peripheral edgeof the wafer, and wherein a front surface of the wafer is divided into aplurality of 2 mm×2 mm square areas, a PV value of each of the areas isevaluated, and the maximum PV value among the PV values for allevaluated areas is 20 nm or less.
 13. A wafer with at least one mirrorpolished surface, wherein one main surface of the wafer has aconfiguration that an SFQRmax is 0.10 μm or less, wherein said wafer hasno inflection point from the central portion of the wafer to 2 mm fromthe peripheral edge of the wafer, and wherein a front surface of thewafer is divided into a plurality of 2 mm×2 mm square areas, a PV valueof each of the areas is evaluated, and the maximum PV value among the PVvalues for all evaluated areas is 18 nm or less.
 14. The wafer accordingto claim 12, wherein a back surface of the wafer is mirror polished. 15.The wafer according to claim 13, wherein a back surface of the wafer ismirror polished.